Carleton University student specialising in FPGA/ASIC design, RTL verification, and systems-level programming. I debug at the waveform, not just the terminal.
Maintain enrollment, tuition, and financial records for two schools; build SQL queries and exports for operational reporting. Independently designed, built, and now maintain the school's production registration/payments/check-in platform (see AlBayan School Management Platform above).
Co-own and help run day-to-day business operations and finances for the shop.
Production platform used daily by a real school: an admin panel for staff, a parent portal for registration and payments, and a teacher portal, with automated payment matching from e-transfer emails and duplicate/unmatched-payment detection.
Traffic-light controller in SystemVerilog RTL as a finite state machine with adjustable phase timers, pedestrian and emergency requests, and fail-safe logic that blocks conflicting green signals. Self-checking testbench with assertions flagging unsafe signal combinations during reset, state changes, and requests.
Combinational Verilog that converts numeric inputs into digits and decodes each into its seven-segment pattern, prototyped in Logisim to confirm truth tables before writing HDL. Synthesized in Vivado, pin-mapped via an XDC constraints file, and tested on Blackboard FPGA hardware against expected values.
Offline system built with a four-person team that communicates emergency messages through timed light pulses, captured by camera and decoded in C on a Raspberry Pi 5 running QNX. Built the local Python server and dashboard that turns decoded pulses into readable status messages, all without internet access.
Analyzed an existing Java game engine with a three-person Scrum team to document the as-is system and define the to-be system: two-week sprints in Jira, and a requirements specification, user stories, and measurable quality targets in Confluence, each traced back to source code.